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  165 mhz, high performance hdmi transmitter data sheet adv7513 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features general incorporates hdmi v1.4 features, including 3d video support 165 mhz supports all video formats up to 1080p and uxga supports gamut metadata packet transmission integrated cec buffer/controller compatible with dvi v1.0 and hdcp v1.4 video/audio inputs accept logic levels from 1.8 v to 3.3 v digital video 3d video ready programmable, 2-way color space converter supports rgb, ycbcr, and ddr supports itu-656-based embedded syncs automatic input video format timing detection (cea-861-e) digital audio supports standard s/pdif for stereo linear pulse code modulation (lpcm) or compressed audio up to 192 khz high bit rate (hbr) audio 8-channel uncompressed lpcm i 2 s audio up to 192 khz special features for easy system design 5 v tolerant i 2 c and hot plug? detect (hpd) i/os, no extra device needed no audio master clock needed for supporting s/pdif and i 2 s on-chip mpu with i 2 c master performs hdcp operations and edid reading operations on-chip mpu reports hdmi events through interrupts and registers applications gaming consoles pcs dvd players and recorders digital set-top boxes a/v receivers functional block diagram tx0+/tx0? adv7513 cec cec controller/ buffer audio data capture spdif video data capture registers and configuration logic hdcp and edid microcontroller hdcp keys hdcp encryption cec_clk i2s[3:0] mclk lrclk sclk d[23:0] vsync hsync de clk hpd int sda scl 4:2:2 4:4:4 and color space converter i 2 c slave i 2 c master tx1+/tx1? tx2+/tx2? txc+/txc? ddcsda ddcscl 10225-001 tmds outputs figure 1. general description the adv7513 is a 165 mhz, high-definition multimedia interface (hdmi?) transmitter that is ideal for dvd players/ recorders, digital set-top boxes, a/v receivers, gaming consoles, and pcs. the digital video interface contains an hdmi v1.4/dvi v1.0- compatible transmitter and supports all hdtv formats. the adv7513 supports hdmi v1.4-specific features, including 3d video. the adv7513 also supports x.v.color?, high bit rate (hbr) audio, and the programmable auxiliary video information (avi) infoframe features. with the inclusion of hdcp, the adv7513 allows the secure transmission of protected content as specified by the hdcp v1.4 protocol. the adv7513 supports both s/pdif and 8-channel i 2 s audio. its high fidelity 8-channel i 2 s interface can transmit either stereo or 7.1 surround audio up to 768 khz. the s/pdif interface can carry compressed audio, including dolby? digital, dts?, and thx?. fabricated in an advanced cmos process, the adv7513 is provided in a 64-lead lqfp surface-mount plastic package with exposed pad and is specified over the ?25c to +85c temperature range.
adv7513 data sheet rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical specifications ............................................................... 3 absolute maximum ratings ............................................................5 ? explanation of test levels ............................................................5 ? esd caution...................................................................................5 ? pin configuration and function descriptions ..............................6 ? applications information .................................................................8 ? design resources ..........................................................................8 ? outline dimensions ..........................................................................9 ? ordering guide .............................................................................9 ? revision history 11/11revision 0: initial version
data sheet adv7513 rev. 0 | page 3 of 12 specifications electrical specifications table 1. parameter symbol temp test level 1 min typ max unit digital inputs data inputs, video and audio, cec_clk input voltage, high v ih full vi 1.35 3.5 v input voltage, low v il full vi ?0.3 +0.7 v input capacitance 25c viii 1.0 1.5 pf cec_clk frequency 2 full viii 3 12 100 mhz cec_clk accuracy full viii ?2 +2 % ddc i 2 c lines (ddcsda, ddcscl) input voltage, high v ih full iv 1.4 5.5 v input voltage, low v il full iv ?0.3 +0.7 v i 2 c lines (sda, scl) input voltage, high v ih full vi 1.4 5.5 v input voltage, low v il full vi ?0.3 +0.7 v cec pin input voltage, high v ih full vi 2.0 5.5 v input voltage, low v il full vi ?0.3 +0.8 v output voltage, high v oh full vi 2.5 3.63 v output voltage, low v ol full vi ?0.3 +0.6 v hpd pin input voltage, high v ih full vi 1.3 5.5 v input voltage, low v il full vi ?0.3 +0.8 v thermal characteristics thermal resistance junction-to-case jc full v 20 c/w junction-to-ambient ja full v 43 c/w ambient temperature full v ?25 +25 +85 c dc specifications input leakage current i il 25c vi ?1 +1 a power supply 1.8 v supply voltage (dvdd, avdd, pvdd, bgvdd) full iv 1.71 1.8 1.90 v 3.3 v supply voltage (dvdd_3v) full iv 3.15 3.3 3.45 v power-down current 25c iv 300 a transmitter total power 3 at 1.8 v full vi 256 mw at 3.3 v full vi 1 mw ac specifications tmds output clock frequency 25c iv 20 165 mhz tmds output clock duty cycle 25c iv 48 52 % input video clock frequency full iv 165 mhz input video data setup time 4 t vsu full iv 1.8 ns input video data hold time 4 t vhld full iv 1.3 ns tmds differential swing 25c vii 800 1100 1200 mv differential output timing low-to-high transition time 25c vii 75 95 ps high-to-low transition time 25c vii 75 95 ps vsync and hsync delay from de falling edge 25c iv 1 ui 5 to de rising edge 25c iv 1 ui 5
adv7513 data sheet rev. 0 | page 4 of 12 parameter symbol temp test level 1 min typ max unit audio ac timing sclk duty cycle n/2 is an even number full iv 40 50 60 % n/2 is an odd number full iv 49 50 51 % i2s[3:0], s/pdif setup time t asu full iv 2 ns i2s[3:0], s/pdif hold time t ahld full iv 2 ns lrclk setup time t asu full iv 2 ns lrclk hold time t ahld full iv 2 ns i 2 c interface scl clock frequency full 400 khz sda setup time t dsu full 100 ns sda hold time t dho full 100 ns setup time for start condition t stasu full 0.6 s hold time for start condition t stah full 0.6 s setup time for stop condition t stosu full 0.6 s 1 see the explanation of test levels section. 2 12 mhz crystal oscillator for default register settings. 3 1080p, 24-bit typical random pattern. 4 the video data setup and hold times are measured at 0.9 v. th e relationship between the clock and data is programmable in 400 ps steps. 5 ui is the unit interval.
data sheet adv7513 rev. 0 | page 5 of 12 absolute maximum ratings table 2. parameter rating digital inputs (sda, scl, ddcsda, ddcscl, hpd, pd) ?0.3 v to +5.5 v audio/video digital inputs (d[23:0], mclk, clk, lrclk, cec, cec_clk, spdif, i2s[3:0], sclk, hsync, de, vsync) ?0.3 v to +3.63 v digital output current 20 ma operating temperature range ?40c to +100c storage temperature range ?65c to +150c maximum junction temperature 150c maximum case temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. explanation of test levels i. 100% production tested. ii. 100% production tested at 25c and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25c; guaranteed by design and characterization testing. vii. limits defined by hdmi specification; guaranteed by design and characterization testing. viii. parameter is guaranteed by design. esd caution
adv7513 data sheet rev. 0 | page 6 of 12 dvdd d12 txc? hsync pin configuration and fu nction descriptions 2 3 4 7 6 5 1 8 9 10 12 13 14 15 16 11 47 46 45 42 43 44 48 41 40 39 37 36 35 34 33 38 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pin 1 top view (not to scale) de d0 d1 d2 d3 d4 d5 d6 d7 d8 clk d9 dvdd d10 d11 vsync spdif mclk i2s0 i2s1 i2s2 i2s3 sclk lrclk pvdd dvdd bgvdd r_ext avdd hpd d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 sda scl ddcsda ddcscl txc+ avdd tx0? tx0+ pd tx1? tx1+ avdd tx2? tx2+ int dvdd_3v cec dvdd cec_clk adv7513 notes 1. the exposed pad is the electrical ground for the part and must be soldered to the pcb. 10225-002 figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic type description 1, 11, 31, 51 dvdd power 1.8 v power supply. these pi ns should be filtered and as quiet as possible. 2 vsync input vertical synchronization input. 3 spdif input s/pdif (sony/philips digital interface) audio input. 4 mclk input audio reference clock input. 5 i2s0 input i 2 s channel 0 audio data input. 6 i2s1 input i 2 s channel 1 audio data input. 7 i2s2 input i 2 s channel 2 audio data input. 8 i2s3 input i 2 s channel 3 audio data input. 9 sclk input i 2 s audio clock input. 10 lrclk input left/right channel signal input. 12 pvdd power 1.8 v pll power supply. 13 bgvdd power 1.8 v band gap power supply. 14 r_ext input this pin sets th e internal reference currents. 15, 19, 25 avdd power 1.8 v power supply for tmds outputs. 16 hpd input hot plug detect signal input. 17, 18 txc?, txc+ differential output differential tmds clock output. 20, 21 tx0?, tx0+ differential output differential tmds output channel 0. 22 pd input power-down control and i 2 c address selection. 23, 24 tx1?, tx1+ differential output differential tmds output channel 1. 26, 27 tx2?, tx2+ differential output differential tmds output channel 2.
data sheet adv7513 rev. 0 | page 7 of 12 pin no. mnemonic type description 28 int output interrupt signal output. 29 dvdd_3v power 3.3 v power supply. 30 cec input/output cec data signal. 32 cec_clk input cec clock (oscillator from 3 mhz to 100 mhz). 33 ddcscl control serial port data clock to sink. 34 ddcsda control serial port data input/output to sink. 35 scl control serial port data clock input. 36 sda control serial port data input/output. 37 to 50, 52, 54 to 62 d[23:0] input video data inputs. 53 clk input video input clock. 63 de input data enable signal for digital video. 64 hsync input horizontal synchronization input. epad power the exposed pad is the electrical ground for the part and must be soldered to the pcb.
adv7513 data sheet rev. 0 | page 8 of 12 applications information design resources evaluation kits, reference design schematics, hardware and soft- ware guides, and other support documentation are available under a nondisclosure agreement (nda). for more information, contact atv_videotx_apps@analog.com . other references include the following: ? eia/cea-861-e this technical specification document describes audio and video infoframes, as well as the e-edid structure for hdmi. it is available from the consumer electronics association (cea). ? high-definition multimedia interface specification version 1.4 , a defining document for hdmi v1.4, and the hdmi compliance test specification (cts) version 1.3a are available from hdmi licensing, llc. ? high-bandwidth digital content protection system revision 1.4 , the defining technical specification document for hdcp revision 1.4, is available from digital content protection, llc.
data sheet adv7513 rev. 0 | page 9 of 12 outline dimensions compliant to jedec standards ms-026-bcd-hd 1 16 17 32 32 49 64 48 33 12.20 12.00 sq 11.80 10.20 10.00 sq 9.80 1 16 17 49 64 48 33 pin 1 top view (pins down) bottom view (pins up) exposed pad 03-16-2010-a view a 1.60 max seating plane 0.75 0.60 0.45 1.00 ref 0.15 0.05 0.08 coplanarity 7 0 0.20 0.09 view a rotated 90 ccw 1.45 1.40 1.35 0.27 0.22 0.17 0.50 lead pitch 7.50 ref sq for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 5.10 5.00 sq 4.90 figure 3. 64-lead low profile quad flat package [lqfp_ep] (sw-64-2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adv7513bswz ?25c to +85c 64-lead low profile quad flat package, exposed pad [lqfp_ep] sw-64-2 EVAL-ADV7513-AKZ evaluation kit with hdcp keys 1 z = rohs compliant part.
adv7513 data sheet rev. 0 | page 10 of 12 notes
data sheet adv7513 rev. 0 | page 11 of 12 notes
adv7513 data sheet rev. 0 | page 12 of 12 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). hdmi, the hdmi logo, and high-definition multimedia interface are trademarks or registered trademarks of hdmi licensing llc in the united states and other countries. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10225-0-11/11(0)


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